Apple M5 Pro, Max, and Ultra could ditch much vaunted unified memory architecture for split CPU and GPU designs fabbed on TSMC N3E

Apple only recently announced the new MacBook Pro 14 and MacBook Pro 16 with M4 Pro and M4 Max SoCs, but we are already getting to know of what could be in store for the succeeding M5 lineup next year.

This information comes via known supply chain analyst Ming-chi Kuo, who has predicted some developments on X with respect to Apple’s upcoming M5 series of chips.

According to Kuo, the M5 series comprised of the base M5, M5 Pro, M5 Max, and M5 Ultra will all be fabbed on TSMC’s N3P node, which was prototyped a few months ago. Both the M4 series used in the latest Macs and the A18 / A18 Pro used in the iPhone 16 series are manufactured on TSMC’s N3E process, which itself is a revision from the N3B process that the A17 Pro was made on.

Kuo expects the M5 series to enter into production in 1H 2025 and 2H 2025, with the M5 Ultra starting in 2026.

The analyst also says that the M5 Pro, Max, and Ultra chips will employ a server-grade 2.5D TSMC packaging called System on integrated chips-molding Horizontal (SoIC-mH). SoIC-mH enables Apple to separate CPU and GPU designs while improving yields and thermals.

SoIC is basically TSMC’s version of 3D stacking and hybrid wafer bonding. The advantage with hybrid wafer bonding is that it allows ultra-dense and ultra-short connections between two wafers. SoIC-X is a variant of the technology that is currently used in AMD 3D V-cache.

Interestingly, Kuo mentions SoIC-mH as 2.5D tech, which might mean that 3D stacks are glued horizontally by means of CoWoS or InFO packaging. While SoIC-X is bumpless, SoIC-P is a bumped packaging that allows an N3 wafter to be stacked on top of an N4 or higher chip in a face-to-back (F2B) orientation.

Another intriguing aspect is the separate CPU and GPU design. If true, this essentially means M5 will not use a unified memory architecture (UMA) shared between the CPU and the GPU. UMA has been a hallmark of Apple silicon and is one of the prime reasons behind its performance and energy efficiency. The corollary argument then would be whether this new split design actually translates into real world performance gains without consequential increases in TDP.

That being said, such a split design may help with improved AI inferencing. As such, Apple’s Private Cloud Compute (PCC) is likely to be the biggest benefactor with high-end M5 designs.

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Though a cell and molecular biologist by training, I have been drawn towards computers from a very young age ever since I got my first PC in 1998. My passion for technology grew quite exponentially with the times, and it has been an incredible experience from being a much solicited source for tech advice and troubleshooting among family and friends to joining Notebookcheck in 2017 as a professional tech journalist. Now, I am a Lead Editor at Notebookcheck covering news and reviews encompassing a wide gamut of the technology landscape for Indian and global audiences. When I am not hunting for the next big story or taking complex measurements for reviews, you can find me unwinding to a nice read, listening to some soulful music, or trying out a new game.

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