IBM’s Power11 Processor Architecture at Hot Chips 2025

Third up on today’s CPU track is IBM. Big Blue is at the conference to talk about its latest generation Power architecture chip, the Power11.

IBM starts off by recapping Power. Why it exists, and what IBM’s goals are for the processor and architecture. IBM is very system-focused, rather than focusing on selling just CPUs. 1P and 2P systems, all the way up to 16P “glueless” systems.

Recapping the Power release history, Power10 has proven to be very successful for IBM, “beyond our wildest dreams.” As a result, Power11 is not a substantial change from Power10; it builds upon Power10 rather than replacing large parts of it. This also means that there’s not as much new here as there have been in past Power presentations – or even other Hot Chips presentations.

To note: Power11 systems have already launched. So this Hot Chips presentation is more to bring the crowd up to speed than to blow everyone’s minds with new information.

IBM’s philosophy is fewer, larger cores, and then scaling up the number of cores as necessary.

One of the big changes coming from Power10? The need to integrate AI into the processor cores.

In some respects, IBM was already ahead of the curve here with their matrix multiplication engine in Power10. But, of course, that’s not enough.

Power10 was built on Samsung 7LPE. Power11 stays on 7nm (based on feedback from clients), so there was a focus on speed instead of density. As a result, it’s built on a newer iteration of Samsung’s 7nm technology.

Power11 also goes to a stacked design. IBM is using a silicon interposer, also based on Samsung fab offerings.

Besides making a handful of core architecture changes, there has been a focus on the full system stack for Power11. This means working on everything from quantum safety for resilience against future attacks, up to improving how to go about deploying updates to systems.

Bigger still are the upgrades to the memory subsystem for Power11, which IBM calls their OMI Memory Architecture. The hierarchical memory architecture means that one chip has up to 32 DDR ports of DDR5 memory. 38.4Gbps fabric speeds, ultimately leading to a customized memory form factor, the OMI D-DIMM.

IBM isn’t very bullish on HBM, by the way. Not that isn’t fast (it is), but it’s relatively low in capacity. IBM wants it all: they want 8TB of DRAM and >1TB/second of memory bandwidth. OMI can get there, all building on top of classic DDR5 memory. These OMI buffers add 6 to 8 nanoseconds of latency, according to IBM.

Power11 will also bring improved support for external PCIe accelerators. IBM has their own Spyre accelerator here.

And, of course, IBM isn’t stopping with Power11. The next generation of Power – Power Future – is under development. IBM has to design their next chip with industry shifts in mind, both with regards to use cases and what technologies are available to build future chips. In short, like everyone else, IBM can’t rely on smaller process nodes to deliver large performance and density uplifts.

Besides immediate manufacturing concerns, there’s also a focus on bandwidth. The use of chiplets brings new challenges with regards to how much chip edge (beachfront) property is available. This is made all the more complex when so much bandwidth is needed just to attach the chiplets to each other. OMI is seen as one solution to that.

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